1. Field of the Invention:
This invention relates to semiconductor fabrication, and more particularly to a method for fabricating a capacitor on a field effect transistor (FET) of a dynamic random access memory (DRAM).
2. Description of Related Art:
Typically, one memory cell of a DRAM device stores one binary data through a capacitor formed in the memory cell. The capacitor can be selectively charged or discharged in order to store the binary data. For example, a charged status of the capacitor represents a binary data of "1", and a discharged status of the capacitor represents a binary data of "0". The capacitance of the capacitor depends on an electrode surface of the capacitor, a distance between two electrodes, and a dielectric material between two electrodes. The memory cell also includes a field effect transistor (FET), to which the capacitor is coupled, so as to perform an operation of charging the capacitor or discharging the capacitor. Usually the capacitor is coupled to a source region of the FET. A word line and a bit line are respectively coupled to a gate and a drain region of the FET so as to select the memory cell.
A smaller memory device dimension is always desired by semiconductor manufacturers. In order to reduce memory device dimension, a structure of DRAM has been developed from a two-dimensional structure to a three-dimensional structure, or called a stacked structure. A stacked capacitor includes multiple plates that are stacked up to produce more charge storage surface. This is strongly necessary. When the DRAM dimension is reduced, capacitance of a two-dimensional capacitor is accordingly reduced. A poor capacitance can causes several problems, such as a poor read-out performance, an increase of soft error, or a consumption of power at a low voltage operation. Thus a poor capacitance causes a memory device not to be fabricated in higher density.
It is an effort for semiconductor manufacturers to reduce the memory device dimension with a maintenance of a necessary capacitance. Particularly, it is a main goal to increase capacitance without increasing a horizontal dimension of the FET in the memory cell. A cylinder capacitor belonging to one of three-dimensional structures is proposed because the cylinder capacitor can be formed with a better stack density. Both an inner surface and an outer surface of the cylinder capacitor can be effectively used to form electrodes so that the cylinder capacitor is very suitable for a DRAM with memory capability of 64 Mb or higher.